Evaluation Methodology for Single Electron Encoded Threshold Logic Gates

Single Electron Tunneling (SET) is an emerging technology, with a switching behavior which is completely different from MOS technology. The ability to control the transport of individual electrons within SET circuits creates the conditions for Single Electron Encoded Logic (SEEL). Although it is expected that, when compared with other approaches, SEEL circuits have both reduced delay and reduced energy consumptions, a method for evaluation is required. This paper proposes a methodology to evaluate delay, power consumption, maximum fanin, and maximum fanout for buffered SEEL linear threshold gates. Furthermore, we discuss the implications of the proposed methodology on practical networks of such gates. We estimate that buffered threshold gates operating at room temperature can potentially switch with a delay of 6 ps and have a packing density of 10^ gates per cm^.